Integrated circuits having bipolar and MOS transistors formed on the same semiconductor substrate have many uses in the electronics industry and are therefore in great demand. One significant advantage of such devices is that they combine the high power and fast switching speeds of bipolar devices with the high density and low power consumption of MOS transistors. The diversity of uses for such BiCMOS devices has fueled a surge toward fabricating faster, denser and more powerful integrated BiCMOS devices by more individual device enhancing manufacturing processes.
When forming devices using a BiCMOS manufacturing process, care is taken to minimize the number of masks employed therein to lower the manufacturing costs. Therefore efforts are made as often as is practicable to integrate the use of regions typically utilized for CMOS/DMOS devices as regions in a bipolar device, and vice-versa. While such integration does serve to minimize manufacturing costs, in some cases the integration causes performance tradeoffs to be made.
For example, prior art FIG. 1 illustrates an NPN type bipolar transistor 10 fabricated using a BiCMOS type fabrication process. The transistor 10 has an n-buried layer (NBL) 12 that is formed in a lightly doped P-type substrate 14. A P-type epitaxial (epi) layer 16 is then grown over the NBL 12 and the substrate 14. A deep N+ring 18 is then formed by performing either an N-type implant or N-type thermal deposition in the epi 16. The deep N+ring 18 couples down to the NBL 12 to, form a collector region 20. The deep N+ring 18 also defines therein an isolated base region 22 comprising the P-epi. The N+region 18 is usually made a ring to provide isolation and serves as a plug extending down to the NBL region 12 for purposes of making contact thereto. A P-type source/drain implant is then performed to define a base contact region 24 and an N-type source/drain implant is performed to form an emitter region 26, wherein the base contact region is formed concurrently with the formation of PMOS source/drain regions elsewhere, and the emitter region is formed concurrently with NMOS source/drain regions elsewhere, respectively.
The NPN bipolar transistor 10 of prior art FIG. 1 may be employed in various types of applications, and in some applications the transistor breakdown voltage may be an issue. For example, a collector-to-emitter breakdown voltage (BVCEO) of the transistor 10 relies on the base (or epi) thickness. That is, a distance 28 between a bottom of the emitter 26 and a top of the NBL 12 will have a significant impact on BVCEO. Although the epi region 16 is initially thick, the thickness of the epi is reduced at locations where the NBL is present due to an up-diffusion 30 of the NBL. The thin epi 16 in that region limits transistor BVCEO by letting the space charge region at the NBL and epi junction reach the emitter during device operation, disadvantageously resulting in a punch-through breakdown condition.
If the epi layer thickness could be increased, or the NBL thickness could be reduced, the transistor BVCEO can be increased. The epi and NBL thicknesses, however, are fixed uniformly across the die for the standard BiCMOS process, and thus any local adjustments thereof would require additional masks and/or processing steps. Such additional actions are disadvantageous when attempting to minimize costs in the fabrication process.
Another NPN type bipolar transistor device fabricated in a standard BiCMOS manufacturing process is illustrated in prior art FIG. 2, and designated at reference numeral 50. The transistor 50 has the NBL 12 fabricated in the substrate (p-sub) 14 and the epi layer 16 is formed thereover in a manner similar to that described above. Deep N+regions 18 are formed down to the NBL 12 and a deep n-well region 52 is formed in the P-epi 16 down to the NBL as illustrated. Concurrently, deep n-well regions are formed elsewhere on the die and are utilized for various purposes, for example, as high voltage PMOS transistors' tank region.
Once the deep n-well region 52 is formed, a shallow P-well region 54 is formed in the deep n-well to form the base region 56. Therefore the NBL 12, deep N+region 18 and the deep n-well 52 together form the collector 58 of the bipolar transistor 50. N-type and P-type source/drain implants are then performed to form the emitter region 60 and the base contact region 62, respectively.
The bipolar transistor 50 has a poor gain, which is sometimes referred to as the transistor β or HFE. When using the BiCMOS process described above, the N-type source/drain region 60 which forms the emitter is quite shallow (for CMOS/DMOS optimization), and the shallow p-well 54 has a high doping concentration, is rather deep, and has a slight retrograde profile for CMOS/DMOS purposes, and these factors contribute to poor bipolar transistor gain. That is, a depth 64 of the heavily doped shallow p-well 54 and the shallowness of the emitter (NSD) 60 results in a depth difference (or base width) 66 that is relatively large, thereby resulting in a low gain. This is disadvantageous in transistor applications where a high gain is important or desired.
Additionally, vertical PNP transistor devices isolated from a substrate do not exist typically in BiCMOS (LBC) technologies. As mentioned above, such technologies are CMOS/DMOS optimized and the bipolar transistors are built using CMOS/DMOS masks to keep costs low. As such, devices produced thereby experience some of the aforementioned deficiencies. Some vertical PNPs do exist, however, but these PNPs are substrate PNP devices which inject current into the substrate and cause undesirable substrate debiasing and latchup.
Lateral PNPs similarly have undesirable characteristics in that they are large and slow. For example, lateral PNPs can measure between about 20 to 30 micrometers and can operate at an Ft of less than 100 mega-hertz. Lateral PNPs also require deep N isolation to mitigate leakage and collector resistance. Moreover, conventional poly-emitter PNPs require two to four additional masks to be formed, thus adding expense to the manufacturing process. In particular, one conventional technique for forming a self-aligned poly-silicon-emitter PNP transistor requires three additional masks in a CMOS/DMOS optimized BiCMOS process. In such a process respective masks are required for establishing a buried P+ layer (BPL) which serves as a collector region of the transistor, an intrinsic N-base layer and an emitter opening area. Similarly, a poly-silicon-emitter PNP can be formed in a SiGe-base heterojunction bipolar transistor (HBT) process, but such a process is complex and expensive aiming at high performance. Such a process is not, however, cost effective.
Therefore, there is a need in the art for a CMOS/DMOS manufacturing process that allows for optimization of bipolar transistor parameters, and in particular to parameters related to vertical PNP transistors, but does not significantly increase the number of steps and/or masks required in the process.